Setup with the new DE0-Nano-Soc board.

[fotoopa]

The first start with this beautiful new board goes very smoothly. The SPI connection has already been tested. It makes every 14 usec a new scan of the 24 inputs and the 24 outputs. The I2C connection with Fischertechnik's TXT-Controller is also tested and works at full speed. The LCD display with 4x20 char and 4 pages has also been started. So I can already see the results of e.g. the 24 input lines of the first SPI box on this display. I have chosen to mount an Arduino shield on the provided I/O pins of the DE0-Nano_Soc board. There is the I2C connector and 2 SPI connections for read and write of 24 in-outs. Also 6 analog signals from the ADC converter are available on this shield. The software is transferred from the old version DEO-Nano. In most cases I only had to rearrange the pinout. The FPGA is now much larger and there is also more memory available. In the other half of the chip you still have the dual core ARM A9 processor with included Linux. It also works but I don't use it yet. When the ARM processor is not in use the current is around 380 mA at 5V. With Linux active this increases to over 800 mA. When both are active together the temperature of the chip rises quite a bit. I am going to add 2 more SPI lines, then I have 96 in and out lines at my disposition.


HD pictures on Flickr: https://www.flickr.com/photos/fotoopa_hs/50079576122

I'm going to add a lot of extra hardware. For example, I have a new SPI modular board in development for 24 inputs and 24 outputs each. There will be options to control motors (6 motors per SPI block, 3 x TB6612 chips) or 24 servo lines or 3 stepper motors. On each I/O box there are always 24 inputs so that the total number of inputs is brought to 96 lines.refrech cycle is 14 usec. All motor controllers have 4 modes so they can also use quadrature decoders for positioning. These encoders work up to well above 30 Khz input signals. With such an FPGA, all functions can work simultaneously at full speed. Timing is never a problem!
For now, I only use 3% of the chip!
Frans.

[fotoopa]

More digital fast speed inputs (96) and outputs via spi modules.
I made a basic spi module with 3x 74hc165 and 3x 74hc595 chips. On this basic module I can place different types of outputs. In total I provided 4x spi connections on the DE0_Nano soc board. With the existing step motor module together I have 96 digital inputs that can be read simultaneously. The readout takes 14 us so I can detect 35 KHz input signals and send pulses to the outputs every 14 usec.

HD on Flickr: https://www.flickr.com/photos/fotoopa_hs/50198760866


HD on Flickr: https://www.flickr.com/photos/fotoopa_hs/50198215993

To test the outputs I made a 24 bit counter. The counter is increased every 14 usec. With the logic analyser these outputs are perfectly visible. I have placed a trigger on bit20 so you can see the transition of the counter. On the trigger signal you can see the value of 1048575 going to 1048576.


UHD on Flickr: https://www.flickr.com/photos/fotoopa_hs/50198760796

All input and output signals can be processed by the TXT via I2C. A 4x20 char LCD display is connected to the FPGA. There all digital inputs can be seen in real time. A lot of I/O pins remain free. A part is sent to 4 BNC conectors for the scope measurements, 8 lines are made available for the logic analyser.
In addition there are some small auxiliary modules like the I2C connector connector, key board for 6 keys, 10 pin and 16 pin output connector for free signals from the FPGA module. There is a 40 pin connector output for the spi buffers and one for the 36 free I/O pins on the 2nd FPGA connector.
Now I need to draw the mounting boxes for the 3D printer.

Frans.

[PHabermehl]

How could I miss this post so far???

Frans,
I just don't know what to say. I'm impressed again. What is this fantastic controller hardware intended for? Another expansion of your marble run?

Kind regards
Peter

[fotoopa]

I just make these modules for the fun of building something. They are very cheap and useful on all my DE0-nano versions. SPI is very simple and not time critical. The clock may even change between near DC to very high speeds during the transfer. So they are also suitable for micro controllers. In the FPGA, the spi driver is a module, a block of hardware that does nothing but read and write.

In the DEO-Nano soc I have 89 free I/O pins. Functionally these I/Os are the same. You don't have to use a specific pin to use a certain function. The base is very simple, 24 in, 24 out. What you do with it is up to you, not the driver. Because you always have 24 inputs this is very practical to have inputs that are linked to for example the motor function on the same connection box. In the meantime I have ordered extra TB6612 modules so I have 12 motors at my disposal. For the motors I use a lot of quadrature decoders. They fit directly on the motor box. They can process encoder speeds up to 35 KHz. Due to the FPGA hardware there is no timing limitation when using multiple modules simultaneously.

I haven't decided on a real new application yet, but I will. Soon there will be a new 4 channel scope. My current 2 channel scope is too little. The next weeks I will first make the 3D print boxes for the modules. I also need to order some parts to connect the power supplies and the spi cables. But this week the 3 grandchildren are here on holiday. I can't build much then unless little Fischertechniek balls tracks.

I don't really need all this, building the modules is just to keep me busy with something.

Schematic and electrical components of the spi module:


HD on Flickr: https://www.flickr.com/photos/fotoopa_hs/50209854656


HD on Flickr: https://www.flickr.com/photos/fotoopa_hs/50210130577

update film pos for the pcb:


Org full 1000 dpi film on Flickr: https://www.flickr.com/photos/fotoopa_hs/50214046107

Film pos 1000 dpi format for pcb.
Note:
There is a small error: pin 10 IC2 and C3 need to connectted to the +5V See pic:
https://www.flickr.com/photos/fotoopa_hs/50209854656
This is the print side. Place the film on the pcb with the text readable for exposure. PCB is a layer(layer16) at the bottom, all components at the top except all SMD elements.
Frans.

[fotoopa]

Basic housing for 6x motor control. Now I have to 3D print the cover and assemble everything. SPI refresch cycle is 14 usec. Besides the 6 motor outputs there are 24 digital inputs. These are connected via the cover. On top of that there is a rotary encoder, 4 pushbuttons and 2 leds that indicate whether 5V or 9V is connected to the module.
And yes I know those long screws in the side plates still have to be replaced by shorter ones!
The 9V power connector is made double (in-out). This way you can connect multiple boxes to the same 9V power supply.


HD version: https://www.flickr.com/photos/fotoopa_hs/50248863522

The other modules ( servo, power outputs) are also ready for final assembly. I am still waiting for the delivery of some parts. Then the additional photos will follow.

Frans.

[fotoopa]

Final assembly of the DE0-nano soc board for the fischertechnik control unit. Different connections can be provided via separate side plates. Because of this I have a more more flexible assembly. The TXT controller is connected via I2C. On the backside are already 4x SPI connectors and the I2C connector.

The LCD 4x20 char display is already on the first part of the top plate.On the second part are a few more keys, the IR detector and 2 rotary encoders. The small front plate already has 4x BNC connectors for the pico scope and 4 pot meters for analog settings.



HD picture: https://www.flickr.com/photos/fotoopa_hs/50281344651

Only half of the chip is used as I do not use the Linux kernel. I don't have enough knowledge to actively use this part as well. By turning off this kernel I save 0.5A on the chip. This makes the temperature much lower. On the FPGA side I still have a lot of free I/O pins available. These I/O's can process signals above 50 MHz. If I have an extra function for this a little later I can connect it via the side plates on the box. Signals for the Logic analyser (16) and the pico scope (4) are already provided. The housing is 3D printed. I also provided outputs for the ws2812b leds 2 circuits each up to 256 leds.

Frans.

[fotoopa]

The harware with the DE0-nano soc module for the TXT Controller is ready.

Controller with DE0-nano soc module. This controller works together with the TXT controller of Fischertechnik via an I2C connection. The TXT is connected to the PC. With this own controller a lot of extensions are possible. Also the processing speed of the different serial modules is much higher. There are 5 spi lines available. Each serial line has 24 digital inputs. Outputs are according to the module and are motors, servo's, stepping motors, power outputs. The spi lines work with a clock of 2MHz so all inputs and outputs are processed in 14 usec. With the 5 spi lines up to 120 inputs are read. A real time overview is shown by an LCD display of 4x20 characters. Via the rotary encoder button 4 different pages can be selected. A second rotary encoder button selects the spi channel. There are 6 additional keys available. At the top is an IR receiver. A remote control is available with 40 keys.

To be able to follow the operation of the FPGA 17 outputs are made for the logic analyser and 4 for the picoscope. This way it is possible to bring out any internal signal within the FPGA for the measurements.

There are 4 analog inputs with a range of 10V. There are also 4 pot meters available for an analog setting. These have a resolution of 12 bits and are read out every 140 usec. These values are also available for the TXT Controller via the I2C connection. 2 BNC connectors are available for a digital clock up to 50 MHz. These can be made as input or output.

On the right side there is a connection for 2 circuits with neopixel leds each up to 256 leds. A separate 5V power connection is provided for this purpose.


HD flickr:https://www.flickr.com/photos/fotoopa_hs/50367267093


HD flickr: https://www.flickr.com/photos/fotoopa_hs/50368124452


HD flickr: https://www.flickr.com/photos/fotoopa_hs/50368124387

Most functions have already been tested with the TXT Controller via the I2C connection. I only use the FPGA part of the DE0-nano soc. I switched off the second part with the linux kernel because I don't have the necessary knowledge to write software for it. The kernel is available for the module and can be enabled if desired.

Frans.

[fotoopa]

With the new acquisition, a 4 channel analog scope, it is again easier to make measurements. The scope has a bandwidth of 50MHz and a sampling up to 1 Gs/sec. An extra large buffer makes a deep analyze possible. The scope is connected to 4 coax 50 ohm cables. To have no extra distortion of the signals on the scope, a line adjustment on the 4 outputs of the FPGA module is made.


HD on Flickr: https://www.flickr.com/photos/fotoopa_hs/50389696526


HD on Flickr: https://www.flickr.com/photos/fotoopa_hs/50389871862


UHD on Flickr: https://www.flickr.com/photos/fotoopa_hs/50389696456

Now I am testing the control of 12 motors. For this I use 2 spi lines. On each spi line there are 24 inputs.They can be used for the quadrature counters, home point or for the end switches. I also have 17 outputs for the logic analyser. These can be used together with all other measurements and/or programs.

Frans.

[fotoopa]

Testing of the spi motor module.

The module contains 3 TB6612 motor drivers to control 6 motors. Full control of the motors is done in the De0 nano soc module. The commands are sent by the TXT controller over the I2C connection. The motors get support for quadrature encoders, min and max switch, home switch and calibration. The position counter is kept in the FPGA module. The TXT only specifies the soll, Ist, speed, braking zone and braking speed. For this reason, the TXT doesn't have a lot of work to handle a lot of motors. I now have 2 spi modules each for 6 motors. If necessary I can add more modules as I have 5 spi lines at my disposal.

The spi module has an external input for the 9V power supply. A second connector makes it possible to forward the power supply to the next module. An extra switch can turn off the 9V in the module.

Each motor can work in one of the 5 modes. These are:
mode 0 :
Single start, stop, dir and speed.
mode1 :
Position control with 1 motor impulse encoder, counting on the positive edge.
mode 2 :
Position control with 1 motor impulse encoder, counting on the negative edge.
mode 3 :
Position control with 1 motor impulse encoder, counting on both edges.
mode 4 :
Position control with motor quadrature encoders.

Mode 1 to mode 4 also have a brake zone and a brake speed. All parameters are given by the TXT.
The module contains 2 extra leds. When the external voltage is 5V only 1 led is lit. If the external power supply is higher than 6.5V the 2 leds are lit.


HD picture Flickr: https://www.flickr.com/photos/fotoopa_hs/50401530377


HD picture Flickr: https://www.flickr.com/photos/fotoopa_hs/50401372836

Frans.

[PHabermehl]

Frans,
I'm speechless... I'm close to believing that one day you'll present us with a homebrew ft based nuclear fusion reactor...

-----------
Frans,
ich bin sprachlos. Ich bin nahe dran zu glauben, dass Du uns eines Tages einen selbstgebauten ft-basierten Fusionsreaktor präsentieren wirst...

[fotoopa]

I'm close to believing that one day you'll present us with a homebrew ft based nuclear fusion reactor...

Hi Peter, it won't run that fast. I'm just past 77 years old. Everything I make now is just for fun and to keep me busy. I don't need it at all.
You may think why you need all these inputs for. With 5 modules I have 120 inputs available. But a really good motor control with quadrature encoders, min and max switches and calibration point need 6 inputs per motor.

The next module I am going to test is the 24 servo module. I just need to connect the top side to the base and the test can start. Later many other functions will follow because I still have more than 20 I/O pins unused on the FPGA. These can all handle very high speeds, as input or output, since they are directly connected to the FPGA. Measuring high speed input pulses up to 20 nsec is no problem at all.

Frans.

[MasterOfGizmo]

Hey Frans,

I really enjoy your postings. Your design always reminds me of russian military technology: The outside looks pretty robust and uses massive switches and connectors and on the inside you have insane logic and computing power.

I sometimes wonder if you are really aware what level of sheer power you have there. This board is heavily subsidized by Intel. Try to find a än official dealer for the FPGA alone will give you a price significantly higher than the one you paid for the entire de0 nano. This chip is expensive and powerful.

This FPGA is big enough to hold several complete commodore amiga computers inside. People are even implementing complete PCs inside this chip. Also be aware that the clock limits you sometimes mention are all due to the logic chips you are using. The FPGA can easily operate its IOs at several hundred Megahertz. When doing differential IO you can easily go way into the ghz range. This chip can e.g. directly generate pcie or hdmi signals.

And the arm part is what makes this FPGA so different. You just get an additional complete linux pc for free. You could just replace the TXT in your setups by this much more powerful component which lives in a small corner of that FPGA.

Your experiments are cool. But you have barely scratched the surface when it comes to the capabilities of this chip/board. Especially the combination of the FPGA side and the Arm core allow for something far beyond anything people have used to control a fischertechnik model. You can run an entire operating system with a decent user interface on the arm and at the same time implement powerful hardware controllers in the FPGA side.

Looking forward to see what use cases you come up with in the future.

[fotoopa]

I sometimes wonder if you are really aware what level of sheer power you have there. This board is heavily subsidized by Intel. Try to find a än official dealer for the FPGA alone will give you a price significantly higher than the one you paid for the entire de0 nano. This chip is expensive and powerful.

Yes, that's exactly what I've seen. So you can never build the hardware yourself.

This FPGA is big enough to hold several complete commodore amiga computers inside. People are even implementing complete PCs inside this chip. Also be aware that the clock limits you sometimes mention are all due to the logic chips you are using. The FPGA can easily operate its IOs at several hundred Megahertz. When doing differential IO you can easily go way into the ghz range. This chip can e.g. directly generate pcie or hdmi signals.

The limitation comes from me because I can only make simple single-sided pcb. So I cannot use differential I/O. I have already gone through the PLL settings and idd are very high in frequency.

And the arm part is what makes this FPGA so different. You just get an additional complete linux pc for free. You could just replace the TXT in your setups by this much more powerful component which lives in a small corner of that FPGA

This is a part of which I have hardly any knowledge, certainly not enough to carry out tests with. I did start up the linux kernel and it works perfectly. However, I do not have the experience and knowledge to write a decent program in C. My dream was that one day I could find someone who could also support this part. I was convinced that you would be able to include the whole TXT in it. However, the power of the chip increases considerably. This causes the temperature to rise quite quickly and it would be advisable to provide some minimal cooling.

The FPGA is extremely powerful. I now only use 23% of the logic elements. If you know that there are already 12 motor unit insert with full autonomous control, in addition to the 5 spi I/O lines at full speed, the 24 servos, the 120 digital inputs, the 8ch analog 12 bits, the LCD display, the scope and logic analyzer lines that you realize that there is much more possible. If I need something extra now I write a small verilog routine a little later the function is available.
Unfortunately, very few people use FPGAs for the hobby. Others who do use it work professionally but you don't see them with Fischertechnik.

Frans.

[MasterOfGizmo]

The limitation comes from me because I can only make simple single-sided pcb. So I cannot use differential I/O.

I don't see the relationship between differential IO and the single sided PCB. Actually staying on one side makes it easier to cope with delays and capacities. If a signal can travel through several meter long cables and can pass a few cheap connectors then it can sure travel a few cm over single sided pcb, Just try it. Hacking your own hdmi signal is really a funny experience.

The FPGA is extremely powerful. I now only use 23% of the logic elements.

You just confused me with that number. 23% sounds pretty much for what you are doing with that board. The de0 nano (non soc) uses a 22kLE cyclone iv while your de0-nano-soc even has a 40kLE cyclone v.Using 23% of that is pretty much. Are you sure you aren't accidentially implementing ram buffers in logic or the like? Or you may be missing some proper fitter optimizations? You should be able to do much more than controlling a few motors and a text LCD in 10.000 LEs. That's roughly what's needed to implement a complete 8 bit home computer inside an FPGA.

the scope and logic analyzer lines

In many years of FPGA development i cannot remember having connected the scope or the LA to an FPGA at all. Why don't you use signaltap? It beats any logic analyzer by far. And a scope? What do you use a scope on an FPGA for?

Unfortunately, very few people use FPGAs for the hobby.

Many do. I'd say 90% of the DE10 Nano (the big brother of your board) out there are used by hobbyists. Just google for "MISTer fpga" ...

Very interesting that the DE0-SOC also has temperature problems. People are facing the same with the DE10 Nnao while e.g. my old trusty 3c25 Cyclone III in my MIST does not get warm at all. Interesting to hear that even the smaller 40kLE-SOC version in the DE0 Nano gets hot if the SOC part is not used at all. That's actually pretty annoying. Things that get warm also draw much power ...

[vleeuwen]

Nice piece of effort.
And your are enjoying your hobby too.
Thanks for sharing it with us.

[fotoopa]

@Vleeuwen
Thanks a lot!
If I have a very small part of your knowledge I could also start up the Linux part. At my age it is no longer feasible for me to learn this knowledge. I suspect this will be one of my last small projects. Too many limitations, diabetes, bad eyes, oblige me to less activity.

@ MasterOfGizmo
For differential I/O I have no planned application. Therefore it is not directly on my list.
In terms of utilization, on my previous DE0-nano board it was 10,734 / 22,320 ( 48% ) LE and 4836 registers. With the soc board this is now 3,638 / 15,880 ( 23 % ) ALMs. All memory is still free as well as all DSP blocks. I think the utilization is pretty good. A very large part is taken up by the I2C connection with the TXT controller. There I have 512x8 bit registers for data exchange. Everything is read and write on the TXT side. The 5 spi lines also consume some registers. These are all 24bit registers and are equipped with temp registers. That makes 240 registers and another 240 copy registers. The IR detector with space for 40 keys also needs some registers. With the 5 motor control modes a lot of LE are needed. Most of them don't use such a function but if you really work with auto calibration, with homepoint, with min and max point speed, brake distance, brake speed quadrature decoders, yeah, this increases quickly. For each motor I see that 180 ALMs are needed. With 12 motors this will also be a very large number of ALMs. But I don't have to worry. The compilation time is 1'15" on my I9 PC with 32GB ram and 5TB SSD. Loading the .sof file into the FPGA takes a few seconds.

Logic analyser and scope are my best tools. You can use them anywhere. The large buffers allow deep analysis with events that are far apart and where you can still zoom in with high resolution. The scope connected to the FPGA is more like a 4 ch logic analyzer and is mainly used to follow serial protocols of the SPI and I2C. Again, very deep data. The logic analyser was connected because I did not use the 17 free I/O pins. They are available on the side of the box. Hence connecting the LA was a nice alternative to use them temporarily. The 4 scope ch have a multiplexer into the FPGA so I can select up to 8 sources on each channel via 4 buttons on the front panel.

I thought the signaltap for Qartus was not available in the free lite version. I would like to elaborate on that point in order to use it. That can certainly be useful during development. Thank you for reporting this.

Yes I did a little googling on MIST. There was a lot to be found there. But with Fischertechnik I haven't seen anything yet. Most of their applications are in another area that requires more power from the FPGA and are therefore perfectly suited for this purpose.

About the temperature of the chip. It only heats up when both parts, the FPGA + HPS, are active. Then the current is above 800mA while with the FPGA only the current is only 370mA. With only the FPGA the chip stays cool.

Frans

[MasterOfGizmo]

There I have 512x8 bit registers for data exchange.

There it is! Registers _are_ memory. If you implement 512*8 bit in logic then you'll unnecessarily consume a lot of logic resources. Registers can usually easily be placed in block ram. This will save you a lot of your precious logic blocks.

The large buffers allow deep analysis with events that are far apart and where you can still zoom in with high resolution.
...
I thought the signaltap for Qartus was not available in the free lite version.

Signaltap is available in the free "quartus web edition" which is just a different way of licensing it. I've been using it many times. But you need to sign up with altera/intel. It's really worth that. Signaltap is an excellent tool and you'll probably never use your scope or LA again once you are used to signaltap. Actually I couldn't have done many things without it. Debugging a running CPU is barely possible otherwise. And the fact that it's available for free has driven me to Quartus/Altera in the first place as the equivalent tool from Xilinx is _not_ available for free.

It only heats up when both parts, the FPGA + HPS, are active. Then the current is above 800mA

At what voltage? At 5V? Dunno if your board uses switching regulators. If yes, then this would mean that the full 0.8*5 = 4 Watts are going into the FPGA. No wonder it gets warm ...

And yes, the MIST serves a different purpose. But you can do very funny stuff here. You could e.g. implement a C64 or Atari-ST inside your FPGA and then run Lucky Logic inside it. Wouldn't that be fun? Using the old fischertechnik logic software on a computer running inside the FPGA and controlling your marble runs? I am sure you've used some of those computers back in the day. With that FPGA you could revive those times ...

[fotoopa]

There it is! Registers _are_ memory. If you implement 512*8 bit in logic then you'll unnecessarily consume a lot of logic resources. Registers can usually easily be placed in block ram. This will save you a lot of your precious logic blocks.

No, it's not that simple. There are multiple tasks running simultaneously in the FPGA that need access to different registers. Even with dual ported ram you won't solve it. Otherwise quartus would have done it itself in most cases. I have already written other applications where I can do it and where I use dual ported ram. I am familiar with these problems.

At what voltage? At 5V? Dunno if your board uses switching regulators. If yes, then this would mean that the full 0.8*5 = 4 Watts are going into the FPGA. No wonder it gets warm ..

Yes at 5V, = extra 4W into the chip!

And yes, the MIST serves a different purpose. But you can do very funny stuff here. You could e.g. implement a C64 or Atari-ST inside your FPGA and then run Lucky Logic inside it. Wouldn't that be fun? Using the old fischertechnik logic software on a computer running inside the FPGA and controlling your marble runs? I am sure you've used some of those computers back in the day. With that FPGA you could revive those times ...

Ha yeah that would be nice. For years we had the commodore C64 for our children. Together with then an extra floppy disk unit. But also very nice are the Atari KIM board, even before the commodore C64 (anno 1978), to put it in the FPGA. I started with the "KIM", that was my first hardware board. In the beginning we had to enter the program and data in hex with the keyboard line by line. Later we were able to use the assembler.

Frans.

[MasterOfGizmo]

No, it's not that simple. There are multiple tasks running simultaneously in the FPGA that need access to different registers.

As long as you have enough logic left you can of course continue to do it this way. But that gives you a pretty false impression of the logic usage of your design. That's exactly where we spend a hug amount of time when doing FPGA work: Use the resources in the most sensible way to be able to squeeze as much features into the FPGA as possible. I am sure it is possible to use BRAM here using e.g. separate time slots for the motor controllers to access shared ram.

Even with dual ported ram you won't solve it. Otherwise quartus would have done it itself in most cases. I have already written other applications where I can do it and where I use dual ported ram. I am familiar with these problems.

You are in the lucky position where you have a vast amount of logic resources and don't have to care for efficient usage. That's totally fine. But this also means that the 23% number you gave is way to high and spending some work on an optimized solution would bring that number down significantly.

Together with then an extra floppy disk unit.

Of couse the floppy also needs to be put into the FPGA. Complete with its entire internal logic incl, the second 6502 CPU and RAM and ROM. This is actually a nice example for shared RAM usage. Our implementation of the C64 + floppy 1541 actually uses a single SDRAM for both. And both machines use a time shared approach to access this (external) SDRAM. Not trivial ... but possible.

But also very nice are the Atari KIM board, even before the commodore C64 (anno 1978), to put it in the FPGA. I started with the "KIM", that was my first hardware board. In the beginning we had to enter the program and data in hex with the keyboard line by line. Later we were able to use the assembler.

So far noone has imho implemented the MOS KIM-1 in an FPGA. But that should be very simple. There's a cycle exact 6502 core and the 6530 RRIOT has also been implemented. So you could rebuild the KIM-1 and be the first. And then you could control your marble machine from the KIM! And you could show your grandchildren how you manually pushed single bits when using computers back in the day

[fotoopa]

After quietly rereading everything I will first read the manual about the signal tap in quartus and try to use it. It looks quite powerful. I see that this document contains 213 pages, so a lot of work to read and to use. I now suspect silence on my part for several weeks...

Frans.